The present invention relates to a tunable quadrature phase shifter comprising an input means for inputting an input signal, splitting means for splitting the input signal into two essentionaly orthogonal first and second signals, adding means for adding said first and second signals, subtracting means for subtracting said first and second signals, a first output for outputting a first output signal based on the output signal from said adding means, and a second output for outputting a second output signal based on the output signal from said subtracting means.
Such a phase shifter which provides two output signals in quadrature are used in e.g. mobile communication systems and other radio transmitter and receiver systems where an accurate 90 degrees phase shift is necessary to obtain a sufficient image rejection in the transmitter and to have a correct 90 degrees phase difference between the I (In-phase) and Q (Quadrature-phase) base band phase vector signals in the receiver. In particular, a possible application is the I/Q generation for RC/LC oscillators with large tuning range (xe2x80x9cSonetxe2x80x9d/xe2x80x9cSDHxe2x80x9d applications). Further, such a phase shifter is used in polyphase filters, QUAMs, Low IF/Zero IF receivers as well as Data and Clock Recovery (DCR) and Phase-Looked-Loop (PLL) circuits.
Among the first known techniques for quadrature signal generation is the RC-CR technique shown in FIG. 1. Here, an input signal vin is shifted by xe2x88x92xcfx80/4 to form a first output signal vo1 and by +xcfx80/4 to form a second output signal vo2. The phase difference between the output signals vo1 and vo2 is always xcfx80/2, but the amplitudes of the output signals vo1 and vo2 are equal at one frequency fo=1/(2xcfx80RC) only.
After shifting, limiting stages (not shown in FIG. 1) can be used, but amplitude limiting becomes difficult in the GHz range unless several stages are connected in cascade. This operation is possible in case only zero crossings of the signal are relevant. Nevertheless, there is always a mismatch in gain and amplitude between both the output signals vo1 and vo2 in the two parallel paths. Moreover, due to nonlinear effects, slew-rate (dvin/dt) like AM to PM conversion occurs. When the RC time constant varies with process and temperature, the cutoff frequency at which the amplitudes of both the output signals vo1 and vo2 are equal varies, too. Besides, the mismatch between passive components results also in a phase mismatch.
Another conventional method for quadrature generation is the Havens technique according to FIG. 2. The input signal is splitted into two branches by using a quadrature circuit 2 which has approximately quadrature outputs. The precision of this circuit is not mandatory. These two signals are:
v1(t)=A cos (xcfx89t)
v2(t)=A cos (xcfx89t+xcex8)xe2x80x83xe2x80x83(1).
After each of these two signals vo1 and vo2 is limited in amplitude by a limiter 4 and 5, respectively, these two signals are added by an adder 6 and also subtracted by a subtracter 7. Each of the signals from the outputs of the adder 6 and subtracter 7 are again limited in amplitude by limiters 8 and 9, respectively, to form the output signals vo1 and vo2. The interesting part comes from the fact that a phase imbalance from xcfx80/2 gives afterwards an amplitude mismatch between the two signals v1 and v2 cancelled away by the limiting action. This operation is explained below:                                                         v              ⁢                              xe2x80x83                            ⁢              1                        +                          v              ⁢                              xe2x80x83                            ⁢              2                                =                      2            ⁢            A            ⁢                          xe2x80x83                        ⁢                          cos              ⁡                              (                                  θ                  2                                )                                      ⁢                          cos              ⁡                              (                                                      ω                    ⁢                                          xe2x80x83                                        ⁢                    t                                    +                                      θ                    2                                                  )                                                    ⁢                  
                ⁢                                            v              ⁢                              xe2x80x83                            ⁢              1                        -                          v              ⁢                              xe2x80x83                            ⁢              2                                =                      2            ⁢            A            ⁢                          xe2x80x83                        ⁢                          sin              ⁡                              (                                  θ                  2                                )                                      ⁢                          sin              ⁡                              (                                                      ω                    ⁢                                          xe2x80x83                                        ⁢                    t                                    +                                      θ                    2                                                  )                                                                                  (          2          )                .            
The amplitudes A of the sum and difference signals are equal if the phase shifter has two outputs in quadrature (xcex8=xcfx80/2). Assuming that in the second signal v2 there is an amplitude mismatch of magnitude xcex5, the equation for the second signal v2 reads as follows:
v2=(A+xcex5) cos (xcfx89t+xcex8)xe2x80x83xe2x80x83(3).
The effect of such error is that v1+v2 rotates counterclockwise by "PHgr"1 and v1xe2x88x92v2 clockwise by "PHgr"2. In FIG. 3 the phasor diagram of the signals is shown. The two situations depicted correspond to the situation when no amplitude errors are present (FIG. 3a) and the situation when amplitude errors are present (FIG. 3b). From FIG. 3 one can find the phase errors "PHgr"1 and "PHgr"2 and the local phase error "PHgr"1+"PHgr"2 under the assumption that the amplitude error xcex5 is small when compared with the amplitude A, i.e. xcex5 less than  less than A.
The equations for the phase errors "PHgr"1 and "PHgr"2 are                                                         tan              ⁡                              (                                  Φ                  ⁢                                      xe2x80x83                                    ⁢                  1                                )                                      =                                          ϵ                ⁢                                  xe2x80x83                                ⁢                                  sin                  ⁡                                      (                                          θ                      2                                        )                                                                                                2                  ⁢                  A                  ⁢                                      xe2x80x83                                    ⁢                                      cos                    ⁡                                          (                                              θ                        2                                            )                                                                      +                                  ϵ                  ⁢                                      xe2x80x83                                    ⁢                                      cos                    ⁡                                          (                                              θ                        2                                            )                                                                                                    ⁢                      
                    ⁢                      tan            ⁡                          (                              Φ                ⁢                                  xe2x80x83                                ⁢                2                            )                                =                                    ϵ              ⁢                              xe2x80x83                            ⁢                              cos                ⁡                                  (                                      θ                    2                                    )                                                                                    2                ⁢                A                ⁢                                  xe2x80x83                                ⁢                                  sin                  ⁡                                      (                                          θ                      2                                        )                                                              +                              ϵ                ⁢                                  xe2x80x83                                ⁢                                  sin                  ⁡                                      (                                          θ                      2                                        )                                                                                      ⁢                  
                ⁢                  When          ⁢                      xe2x80x83                    ⁢          ϵ          ⁢                      xe2x80x83                    ⁢                       less than  less than             A                    ⁢                      xe2x80x83                    ⁢          the          ⁢                      xe2x80x83                    ⁢          result          ⁢                      xe2x80x83                    ⁢          is          ⁢                      :                                                        (          4          )                .                                          Φ1          +          Φ2                ≅                  ϵ                      A            ⁢                          xe2x80x83                        ⁢                          sin              ⁡                              (                θ                )                                                                                  (          5          )                .            
The amplitude mismatch xcex5 leads to a phase mismatch. 1% amplitude mismatch generates 0.6xc2x0 in phase. Although this method is better in terms of robustness to errors, the disadvantage consists in the use of the four limiters 4, 5, 8 and 9 which convert amplitude modulation into phase modulation. Another critical disadvantage is that even some amplitude errors are tolerated, the input quadrature generator produces for different frequencies unequal amplitudes. Therefore, when the above described quadrature generation circuit is coupled to oscillators for I/Q processing by tuning the oscillator within an octave for example, the amplitude of the two paths drastically varies.
FIG. 2 shows the closest prior art from which the invention proceeds.
EP 0 707 379 A1 discloses a tunable quadrature phase shifter including two branches each constituted by cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90xc2x0 phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers.
WO 92/11704 A1 describes a quadrature signal generator including a phase-locked loop configuration which comprises a voltage control phase-shift network, limiters, an exclusive-OR phase detector, a low phase filter, a differential voltage to current converter and a loop filter. The voltage controlled phase-shift network generates a phase shift for the differential quadrature signals. The exclusive-OR phase detector determines the phase error between the differential quadrature signals. The phase error is related to a voltage control signal which is coupled back to the voltage controlled phased-shift network to maintain a precise 90xc2x0 phase relationship between the differential quadrature signals.
Due to the control mechanism, both the devices according to EP 0 707 379 A1 and WO 92/11704 A1 require a complex and expensive construction.
Accordingly, it is an object of the present invention to provide a simple construction which avoids the amplitude mismatch and can be used for oscillators with more than one octave frequency tuning.
In order to achieve the above and other objects, according to the present invention, there is provided a tunable quadrature phase shifter comprising an input means for inputting an input signal, splitting means for splitting the input signal into two essentially orthogonal first and second signals, adding means for adding said first and second signals, subtracting means for subtracting said first and second signals, a first output for outputting a first output signal based on the output signal from said adding means, and a second output for outputting a second output signal based on the output signal from said subtracting means, characterized in that said splitting means is provided as an all-pass.
Since an all-pass produces two quadrature signals with equal amplitudes and the gm/C time constant of an all-pass tracks the oscillation frequency (using the same tuning mechanism) of the input signal outputted by the oscillator, the amplitude mismatch is well reduced. This further allows to avoid limiters at the input and also at the output. So, the present invention uses gm/C tuning schemes with inherent I/Q matching.
Preferably, a first output buffer means for buffering said first output signal and a second output buffer means for buffering said second output signal are provided.
A further preferred embodiment of the present invention comprises a first transimpedance converter having its input connected to said input means. A modification of this embodiment still comprises a second transimpedance converter having its output connected to said first output and a third transimpedance converter having its output connected to said second output. The provision of transimpedance converters is recommended in case the input and output signals are provided as voltage signals. Usually, the transimpedance converters are transimpedance amplifiers.
In accordance with a still further preferred embodiment of the present invention, the first and second output buffer means are provided as said first and second transimpedance converters, respectively, since the transimpedance converters have buffering functions, too.
A further preferred embodiment of the present invention is characterized by at least a first transistor with its collector connected to its base and its emitter coupled to a predetermined potential, a second transistor with its base connected to the base of said first transistor and its emitter coupled to said predetermined fixed potential, and a capacitor coupled between the junction of the bases of said first and second transistor and said predetermined potential.
In case the tunable quadrature phase shifter is provided as a differential phase shifter, further preferred embodiment is characterized by at least a first transistor with its collector connected to its base and its emitter coupled to a predetermined potential, a second transistor with its base connected to the base of said first transistor and its emitter coupled to said predetermined potential, a third transistor with its collector connected to its base and its emitter coupled to a predetermined potential, a fourth transistor with its base connected to the base of said third transistor and its collector coupled to said predetermined potential, and a capacitor coupled between a first junction of the bases of said first and second transistors and a second junction of the bases of said third and fourth transistors.
In both recently above mentioned embodiments, the transistors can be npn transistors and/or the predetermined potential is zero (ground).